The construction of interconnection networks is an ongoing challenge, as it must keep in pace with the ever-going increase in volume and speed of the basic microelectronic components. Employing optical communication links in interconnection networks provides increased capacity, but to date, conversion between the electronic and the optical systems has several problems: it is expensive; it involves high energy consumption; and it introduces latency to the link, so as to slow down the communication rate.
As seen in FIG. 1a, the basic components of a digital electronic system 1 are the silicon-based integrated circuits 2, or chips 2, such as digital processors, memory chips, and various auxiliary circuits, including controllers, I/O and multiplexing chips, digital to analog converters, and the like. They also include a large number of special purpose integrated circuits for specific applications. These are mounted onto printed circuit boards 4 (PCB 4) and are interconnected by many layers of electrical conduits, forming the interconnection networks 3. In complex systems, several boards 4 are mounted in racks 5, which are further mounted in cabinets 7. The interconnection network between the boards 4 in the rack 5 and the cabinet 7 is implemented by means of a backplane 6, the core of which is an extremely complex PCB.
Order of magnitude lengths of the interconnection networks 3 within the chip 2 may be about 1 mm. Between chips 2, they may be about 1 cm, within the board 4, they may be about 10 cm, within the cabinet 7, they may be about 1 m, between cabinets, they may be about 10 meters, and between systems 1, they may be about 100 m.
The electronic interconnection network 3 is illustrated in FIG. 1b as a data bus 8. Early buses were literally arrays of parallel connectors 9, configured for transferring the synchronized parallel electronic bits of the digital electronic word. But the term “bus” may also apply to any physical arrangement that provides the same logical functionality as a parallel electrical bus.
The digital processor is characterized by a clock cycle or its inverse, the operating frequency, which define the time for executing a single step in a program. Additionally, the digital processor is characterized by a digital electronic word of a specific word size—a predetermined number of parallel electronic bits, synchronized with the clock cycle.
The highest data transfer rate between a processor and another component of the system 1 is realized when each clock cycle of the processor produces a digital electronic word for transfer. The required transfer rate along each of the parallel conduits of the bus is then equal to the operating frequency of the processor. A slower rate may occur when several steps, requiring several clock cycles, are executed prior to the data transfer. For example, depending on the processor, multiplication may require 3 steps, hence, three clock cycles. Nonetheless, the architecture should be designed to meet the highest data transfer rate.
Yet there are problems with a very high data transfer rate, for example, of the order of 1 GHz or higher along the parallel conduits:
1. for acceptable signal to noise ratio along the conduits, the product, distance X data-rate, has to be maintained comparatively low, and in consequence, transfer of data at very high rates is limited to short distances;
2. adjacent parallel conduits manifest cross talk between them, due to electromagnetic interference, which is especially problematic in massively parallel interconnection networks, and which increases with increasing data transfer rate;
3. massively parallel electrical interconnection networks are associated with high heat generation, which also increases with increasing data transfer rate; and
4. high data transfer rate are generally associated with complex PCB, and as the complexity of the PCB grows, the fabrication-process yield decreases, and fabrication becomes expensive.
With the growing demand to process larger volumes of digital data at ever increasing speeds and the exponential growth in performance of the basic microelectronic components, the interconnection network, implemented as a multilayered complex of parallel electrical conduits, becomes a major bottle neck, slowing the technological progress.
A solution may be optical communication links, which have been found effective in telecommunication, and which may be similarly effective for interconnection networks. In telecommunication, light pulses, propagating in glass fibers, has been proven the most effective method for fast transport of large volumes of digital data over long distances.
While the electronic data is represented in the form of digital, parallel-electronic word, the optical data is organized as a serial string of photonic bits, termed herein, digital, serial-optic word. Thus, conversion between the electronic and optic words requires two processes:
1. conversion between parallel and serial signals, by complex multiplexing or de-multiplexing; and
2. conversion between the electronic and the optic representations of the signals, using fast electronic devices and optoelectronic modulators.
These processes are illustrated in FIG. 1c, which describes a standard interconnection network 10, as known, employing an optical fiber communication link 17, between a transmitting electronic processing element 12 (EPU 12) and a receiving electronic processing element 22. The standard interconnection network 10, which is termed in the art, “point-to-point electronic to optical to electronic (EOE) link,” operates as follows:
1. At a transmitting end 11, a digital, parallel-electronic word 13, produced by a transmitting electronic processing element 12, is multiplexed into a serial string of electrical pulses 15, by a multiplexer 14.
2. The serial string of electrical pulses 15 is then converted into a serial string of photonic bits 20, using a standard, for example, Emitter-Coupled-Logic (ECL) or another standard, as known. The conversion may be performed by means of an optical transmitter 16, at the core of which is a constant-power laser light source 16A and a fast optical shutter 16B, such as an electrooptic modulator 16B or an electroabsorption modulator 16B.3. The serial string of photonic bits 20 is transmitted via the optical fiber 17 toward the receiving end 21.4. At the receiving end 21, an optoelectronic receiver 26 converts optical analog signals, propagating in the optical fiber 17, into electronic digital signals, again using a standard such as ECL or another standard, as known. The conversion is a two step process, employing two apparatus, as follows:
a. a first apparatus, being an optical detector:                i. for converting the optical analog signal to an electronic analog signal; and        ii. for recovering the clock frequency and phase of the digital signal represented by the electronic analog signal; and        
b. a second apparatus, which is essentially a “comparator,” and which has a pre-set threshold level, defined by the standard, for converting electronic analog signals below the pre-set threshold level to bits of 0, and electronic analog signals above the pre-set threshold level to bits of 1, to form the electronic digital signal.
Thus the optoelectronic receiver 26 converts the serial string of photonic bits 20, to a corresponding serial string of electronic signals 25.
5. A de-multiplexing circuit 24 converts the serial string of electronic signals 25 to an electronic vector of parallel bits 23, which is essentially the digital, parallel-electronic word 13, at the input ports of the receiving electronic processing element 22.
The conversion from the parallel signal 13, transferred along a bus of parallel conduits, to the serial signal 15, transferred along a single conduit, increases the required data transfer rate by the number of bits per channel, so that the highest data transfer rate that may be realized is:B=N×f(bits/sec)  [1]where,
N is the number of bits in the digital electronic word 13, and
f is the operating frequency.
For example, given a processor configured for an operating frequency of 1 GHz and a word size of 64 bits, the highest data transfer rate from the processor will be 64 Gb/sec, compared with 1 GHz along each of the parallel conduits of the bus. But the single fiber 17 is capable of meeting this rate and is further capable of meeting significant future expansions. In general, a transmission line is characterized by the product B·L, where B is the bit transfer rate, and L is the length of the transmission line. For example: for a polarization-maintaining, dispersion-shifted, single-mode, optical fiber operating at λ=1550 nm, B·L>2·1012 (bit/seconds)·km per (wavelength) channel, so in principle, it is possible to transfer 100 Gb/sec to a distance greater than 20 kilometers, using such a fiber. This is significantly greater than the bit transfer rate of 64 Gb/sec of the electronic circuit. Moreover, when employing wavelength division multiplexing (WDM), with a single fiber carrying a number of parallel channels of different wavelengths, a transfer rate of approximately 1 Tb/sec per fiber may be achieved. Thus, with WDM, a many fold increase in the bit transfer rate of an electronic system can still be met by a state of the art optical communication link of single fiber.
However, the procedure described in FIG. 1c imposes severe constraints on the efficiency of the communication in massively parallel networks, as it requires conversion of the data from electronic to optical at the output, and from optical to electronic at the input of each node. Additionally, it requires expensive and fast electronic circuitry, and in particular, very fast optical shutters. Furthermore, it involves high energy consumption and introduces substantial latency to the link.